FIG. 1A illustrates an example of a conventional memory system. As shown, a conventional memory system may include a memory controller 100 and a memory module 200. The memory module 200 may further include a plurality of memory devices 200-1, 200-2, 200-x, which may be implemented, for example, by DRAMs.
The memory controller 100 may output an external clock signal ECLK, one or more command signals COM such as a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB and a chip select signal CSB, one or more address signals ADD, and/or one or more data signals DATA to the memory module 200.
The memory module 200 may also output one or more data signals DATA to the memory controller 100. In the example shown in FIG. 1A, the one or more data signals DATA may be composed of a serial stream of 2n bits, represented by [1:2n] DATA11 to [1:2n] DATAxj. As shown in FIG. 1A, a memory device 200-1 may receive the external clock signal ECLK, the one or more command signals COM, the one or more address signals ADD, and the DATA signals DATA 11 to DATA 1j. Similarly, a memory device 200-2 may receive the external clock signal ECLK, the one or more command signals COM, the one or more external address signals ADD, and the DATA signals DATA 21 to DATA 2j, and a memory device 200-x may receive the external clock signal ECLK, the one or more command signals COM, the one or more address signals ADD, and the DATA signals DATA x1 to DATA xj.
As shown, in the conventional memory system of FIG. 1A, each memory device 200-1, 200-2, 200-x may receive or output DATA composed of serial 2n bits during one clock cycle of the external clock signal ECLK. In addition, DATA of j bits may be written or read at the same time.
FIG. 1B illustrates an example of a conventional memory device, for example the memory device 200-1 of FIG. 1A, and associated control logic. As shown, the associated control logic may include an address buffer (ADD BUF) 10, a command decoder (COM DEC) 12, one or more serial-to-parallel converters 14-1 to 14-j (a corresponding to the j in FIG. 1A), one or more parallel-to-serial converters 16-1 to 16-j, the memory cell array 18, a row decoder 20, a column decoder 22, a PLL 24, and/or a control signal generation circuit (CSG Ckt.) 26.
The address buffer (ADD BUF) 10 may receive external input addresses (ADD) to generate row addresses (RA), supplied to the row decoder 20, in response to an active command signal (ACT). That is, the address buffer (ADD BUF) 10 may comprise a plurality of address buffer circuits, each of which receives one external address signal to generate one row address signal (RA). Accordingly, if the memory device 200-1 receives twelve external addresses (ADD) from the memory controller 100, the address buffer 10 comprises twelve address buffer circuits for receiving twelve external addresses and generating twelve row addresses (RA).
The row decoder 20 may activate a main word line enable signal (MWE) corresponding to a plurality of row addresses generated from a plurality of row address buffers so that a desired word line (not shown) may be selected in the memory cell array 18. The address buffer (ADD BUF) 10, which may include a plurality of address buffer circuits for a plurality of external address signals, may also generate a plurality of column addresses (CA), supplied to the column decoder 22, in response to a read command (RE) or a write command (WE) decoded from the one or more command signals COM.
The column decoder 22 may receive a plurality of column addresses to activate a corresponding column select line (CSL). A plurality of bit lines of the memory cell array 18 may be selected in response to the selected CSL so that a plurality of data may be written to or read from the selected memory cells.
As set forth above, the command decoder 12 may generate an active command (ACT), a read command (RE), and a write command (WE) after receiving a plurality of external command signals (COM), for example, RASB, CASB, WEB etc.
Each serial-to-parallel converter (14-1 to 14-j) may receive serial data DATA composed of 2n bit data and output 2n bit parallel data through 2n data bus lines simultaneously to the memory cell array 18, in response to a write command signal (WE) and a plurality of control signals (P1˜P(2n)). If the number of data input/data output pins (DQ) is j, the number of serial-to-parallel converter is also j. In addition, each of the serial-to-parallel converters (14-1 to 14-j) may be coupled to the memory cell array 18 via 2n data bus lines.
Each parallel-to-serial converter (16-1 to 16-j) may receive 2n bit data from a memory cell array 18 in parallel and output 2n bit serial data responsive to a read command signal (RE) and the plurality of control signals (P1˜P(2n)). If the number of data input/data output pins (DQ) is j, the number of parallel-to-serial converters is also j.
The phase lock loop 24 may receive the external clock signal ECLK and perform a locking operation to output an internal clock signal CLK1, which is locked with ECLK. After completing the locking operation, the phase lock loop 24 may output a plurality of internal clock signals (CLK1˜CLK1) to the control signal generation circuit (CSG Ckt.) 26. The control signal generation circuit (CSG Ckt.) 26 may generate the plurality of control signals (P1˜P(2n)).
A disadvantage of a conventional data access technique, such as the one described above, is that it is possible to access only 2n bits of data, for example, 2 bits, 4 bits, 8 bits, etc., during one clock cycle of an external clock signal, for example ECLK.
FIG. 2A illustrates operation of a conventional PLL and control signal generation circuit, for example, PLL 24 and control signal generation circuit (CSG Ckt.) 26 of FIG. 1B. As shown, an internal clock signal CLK1 may be locked with an external clock signal ECLK. The PLL may generate two (or more) internal clocks CLK1/CLK2 which may have twice the frequency of ECLK. A phase difference between CLK1 and CLK2 may be 180°. The control signal generation circuit (CSG Ckt.) 26 may generate four control signals P1˜P4 using various combinations of the two internal clocks CLK1˜CLK2 and ECLK. Accordingly, four data D1-D4 may be written or read through serial-to-parallel converters or parallel-to-serial converters, responsive to each of P1˜P4 during one clock cycle of ECLK. Such a memory device may be said to be operating with a quad data rate (QDR).
FIG. 2B illustrates another operation of a conventional PLL and control signal generation circuit, for example, PLL 24 and control signal generation circuit (CSG Ckt.) 26 of FIG. 1B. As shown, the internal clock signal CLK1 may be locked with ECLK. The PLL may generate four internal clocks CLK1˜CLK4 which have the same frequency as ECLK. A phase difference between adjacent clocks may be 90°. The control signal generation circuit (CSG Ckt.) 26 may generate four control signals P1˜P4 using various combinations of the four internal clocks CLK1˜CLK4 and ECLK to access four data D1-D4 from a memory device during one clock cycle of the external clock ECLK. Such a memory device may be also said to be operating with a quad data rate (QDR).
FIG. 3 illustrates yet another operation of a conventional PLL and control signal generation circuit, for example, PLL 24 and control signal generation circuit (CSG Ckt.) 26 of FIG. 1B. As shown, the internal clock signal CLK1 may be locked with ECLK. The PLL may generate four internal clocks CLK1˜CLK4 which have twice the frequency of ECLK. A phase difference between adjacent clocks may be 90°. The control signal generation circuit (CSG Ckt.) 26 may generate eight control signals P1˜P8 using various combinations of the four internal clocks CLK1 ˜ CLK4 and ECLK to access eight data D1-D8 from a memory device during one clock cycle of the external clock ECLK. Such a memory device may be said to be operating with an octal data rate (ODR).
A disadvantage of conventional data access techniques, such as those described above, is that it is possible to access only 2n bits of data, for example, 2 bits, 4 bits, 8 bits, etc., during one clock cycle of external clock signal.
Therefore, a conventional semiconductor device may include extra pins or pads for receiving and/or outputting data bits for error correction coding (ECC), cyclic redundancy coding (CRC) or data masking (DM). This may require a large chip area and, hence, increase manufacturing cost.